1. Field of the Invention
Embodiments of the present invention generally relate to methods for forming passivation protection for an interconnection structure. More particularly, embodiments of the present invention generally relate to methods for forming passivation protection for an interconnection structure for semiconductor devices to prevent excess oxidation.
2. Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technology challenges for next generation very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of VLSI and ULSI interconnect technology have placed additional demands on processing capabilities. Reliable formation of gate structures on the substrate is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
A patterned mask, such as a photoresist layer, is commonly used during etching structures, such as gate structure, shallow trench isolation (STI), bit lines and the like, or back end dual damascene structure on a substrate. The patterned mask is conventionally fabricated by using a lithographic process to optically transfer a pattern having the desired critical dimensions to a layer of photoresist. The photoresist layer is then developed to remove undesired portions of the photoresist, thereby creating openings in the remaining photoresist.
As the dimensions of the integrated circuit components are reduced (e.g., to deep sub-micron dimensions), the materials used to fabricate such components must be carefully selected in order to obtain satisfactory levels of electrical performance. For example, when the distance between adjacent metal interconnects and/or the thickness of the dielectric bulk insulating material that isolates interconnects having sub-micron dimensions, the potential for capacitive coupling occurs between the metal interconnects is high. Capacitive coupling between adjacent metal interconnects may cause cross talk and/or resistance-capacitance (RC) delay which degrades the overall performance of the integrated circuit and may render the circuit inoperable. In order to minimize capacitive coupling between adjacent metal interconnects, low dielectric constant bulk insulating materials (e.g., dielectric constants less than about 4.0) are needed. Examples of low dielectric constant bulk insulating materials include silicon dioxide (SiO2), silicate glass, fluorosilicate glass (FSG), and carbon doped silicon oxide (SiOC), among others.
During the semiconductor manufacturing process, after a metal CMP process, the underlying upper surface of the metal line formed from the dielectric bulk insulating materials is exposed to air. Prior to the subsequent metallization process to form interconnection on the exposed metal, the substrate may be transferred among different vacuum environments to perform a different processing steps. During transfer, the substrate may have to reside outside the process chamber or controlled environment for a period of time called the queue time (Q-time). During the Q-time, the substrate is exposed to ambient environmental conditions that include oxygen and water at atmospheric pressure and room temperature. As a result, the substrate subjected to oxidizing conditions in the ambient environment may accumulate native oxides or contaminants on the metal surface prior to the subsequent metallization process or interconnection fabrication process.
Generally, longer Q-times allow thicker oxide layers to form. Excess native oxide accumulation or contaminants may adversely affect the nucleation capability of the metal elements to adhere to the substrate surface during a subsequently metallization process. Furthermore, poor adhesion at the interface may also result in undesired high contact resistance, thereby resulting in undesirably poor electrical properties of the device. In addition, poor nucleation of the metal elements in the back end interconnection may impact not only the electrical performance of the devices, but also on the integration of the conductive contact material subsequently formed thereon.
Recently, a metal containing passivation layer is utilized to cover the exposed surface of a metal line formed in interconnects from the dielectric bulk insulating materials. The metal containing passivation layer may minimize exposure of the metal line from the interconnect material to atmosphere/air so as to prevent damage to the semiconductor device. Furthermore, materials selected to fabricate the metal containing passivation layer are often required to provide certain desired degree of conductivity as well as high moisture/contamination resistance so as to serve as a good passivation protection at the interface as well as maintaining low resistivity at the interconnection interface. By utilizing this metal containing passivation layer formed on the metal line, exposure to the air/atmosphere may be minimized. However, in some cases, inadequate selection or utilization of the metal containing passivation layer may result in insufficient moisture or diffusion resistance, or film degradation during the subsequent plasma process, thereby eventually leading to device failure.
Thus, there is a need for improved methods to form an interconnection passivation protection structure with good interface quality control for metal exposure with minimum substrate oxidation.